In design processes for very large scale integration (VLSI) integrated circuit chips, standard features and custom features can be combined to produce a completed design. The balance between use of standard and custom features is a difficult one that affects design costs, risks and time-to-market schedules and is often based on market forces that set performance requirements, unit costs, volume and design life for the finished integrated chip.
As illustrated in FIG. 1, different design process technologies lead to different mixes of time-to-market and performance. In FIG. 1, a vertical axis 100 represents relative performance in terms of speed and complexity of the functions performed by a chip. A horizontal axis 102 represents relative time lengths of the design process for the chip.
A technology known as field programmable gate array (FPGA) typically produces designs indicated at 104 with ranges of relatively low performance, and medium time-to-market. With FPGA technology, an integrated circuit manufacturer places fixed gates in fixed patterns on chips and provides a fixed but “programmable” array of interconnects. The customer can then alter the interconnects on each chip, typically by damaging an interconnect with an overcurrent, to customize each gate array chip for a particular application. Because the “building blocks” for this technology are system gates or other medium scale logic elements, the complexity that can be achieved is limited.
A technology known as application specific integrated circuitry (ASIC) typically produces designs indicated at 106 with ranges of relatively high performance and high time-to-market. With ASIC, an integrated circuit manufacturer provides a library of low to medium complexity cells such as logic gates, counters and latches. The integrated circuit manufacturer also provides or specifies software tools so that a customer can design, simulate and time the customer's circuit. This logical representation is translated into a custom layout and custom interconnect of library and sometimes custom integrated circuits. Once the customer's design is complete, then the integrated circuit manufacturer uses the customer's design to manufacture custom chips with a custom interconnect pattern and also custom cell patterns. The design process is long because of the ever-increasing complexity associated with the open-ended nature of this process.
A design process known as application specific standard product (ASSP) typically produces designs indicated at 108 with ranges of relatively medium performance and low time-to-market. With ASSP, an integrated circuit manufacturer completes the design process for a chip (in much the same manner that a customer would complete a design process for an ASIC). Once the design is complete, then the integrated circuit manufacturer uses the design to make standard chips that are typically sold to multiple customers with similar needs, typically in a particular application niche. The use by multiple customers increases the volume and allows for a larger investment in the design process.
A more recent design process referred to here as a “standardized silicon platform” has a capability to produce designs indicated at 110 with ranges of performance and time-to-market that are comparable to FPGA, ASSP and ASIC, and also has a capability to produced designs in ranges outside of range of capabilities of FPGA, ASSP and ASIC. With standardized silicon platform technology, the manufacturer provides a partially manufactured very large scale integration (VLSI) standard integrated circuit that includes standard slices that are designed to perform complex, high level functions, but which have not had all of their associated interconnect layers completed. The integrated circuit manufacturer provides or specifies software design tools that enable a customer to integrate and customize these complex high level functions, thereby providing a very high level, fast design tool. The customer can also add in the customer's customized circuitry on the same chip. Once the customer's design is complete, the completed chip can be much more quickly produced since a significant portion of the problem is already solved. The time needed to integrate and customize the standardized silicon platform is small in comparison to ASIC technology. High relative levels of performance can be achieved with standardized silicon platform technology.
Within the entire design space, one area that can cause great difficulty across the spectrum of design activities is the generation, management, qualification and testing of clocking and reset circuitry. The standardized silicon platform technology includes the use of clocking and reset circuitry. Clock and reset circuitry is used to generate synchronized clock signals to meet the customer's specification for speed, sequencing, skew and other parameters. It is found however, that in many cases the clock and reset circuitry is done in a way that is not compatible with the capabilities of the design systems available. There are many ways to create and manage these circuits poorly. As a result, they are often not able to meet complex clocking requirements that are unique to each customer's application. In addition, if these circuits are designed outside the capabilities of the design system, severe delays can be and are encountered in the overall development of the circuit. Implementation of complex “ad hoc” clock and reset circuitry is often difficult to test using EDA tools, slows down the circuit design process, and introduces considerable technical risk into the performance of the chip. The “ad hoc” circuitry is difficult to test using standard manufacturing test software tools, leaving potential open loop timing closure problems in the design.
A method and apparatus are needed that provide an increased level of standard clock and reset functionality and that reduce or eliminate the need for “ad hoc” customer circuitry for producing clocks that meet customer specifications.